Semiconductor devices may include several transistor cells arranged in a predefined pattern. For example, in the case of FET (field effect transistor) devices, several source/drain pairs may be fabricated on a substrate and a corresponding gate electrode may be formed over the source/drain pair. In operation, adjacent cells may experience a leakage current at the edge of cell. As a result, adjacent cells may be separated to reduce the overall effect of leakage within the semiconductor device. However, separating adjacent cells results in an increase in the design area of the semiconductor device.